In this position, the candidate will be responsible for the design, development and delivery of complex, high-speed Verilog-based subsystems.
- Developing and documenting micro-architectures.
- Block- and system-level RTL coding.
- Performing checks (Lint, Equivalence checks, CDC…) to ensure the quality of RTL.
- Synthesizing designs and providing timing constraints to the Physical Design team.
- Working with a Verification team to define the test plan and thoroughly verifying a design.
- 5+ years high speed digital design of complex IP and/or CPU Sub-systems.
- Expert in RTL coding, integration, and synthesis.
- Prior experience in all quality checks (e.g.: Lint, CDC…).
- Good understanding and working knowledge of verification and timing closure.
- Able to provide timing constraints and work with PD teams to ensure design meets timing.
- Strong debugging and scripting skills (Perl, Python, Tcl…).
Highly Preferred Qualifications
- Prior experience with RiscV CPU subsystems.
- Experience with low power and multi-power domain design.
- Prior Silicon debug experience.
Education & Experience
- BSEE / MSEE is required.
- Strong interpersonal and communication skills.
- Highly organized and detail oriented.