Senior IC Physical Design Engineer

InspireSemi is developing multi-thousand core RISC-V SoC’s for HPC & AI (High-Performance Computing), engineering/scientific, and graph analytics applications.

In this position, the successful candidate will generate complete IC designs from RTL/netlists and third-party IP blocks, in the latest advanced FinFet process technology nodes.

Job Responsibilities

• Floorplanning, IO pad/bump/pin placement, and power grid insertion
• Automated standard cell placement and routing
• Integrating hierarchal block designs including third-party IP
• Power, performance, and area optimization, working closely with RTL designers
• DRC and LVS verification/debugging
• EM/IR analysis
• Timing signoff

Qualifications

• BS or higher degree in electrical or computer engineering
• 5+ years of experience in automated digital IC design from RTL to GDS
• Experience with advanced process nodes from 12nm down to 4nm and lower
• Excellent EDA tool scripting and problem-solving skills
• Fundamental understanding of electronic design principles and process design rules

Preferred Experience

• Cadence APR toolchain (Genus, Innovus, Pegasus, etc)
• Implementing high-performance CPU cores
• Designing with high-speed digital interface blocks such as PCIe, DDR and HBM
• Designing and verifying large-scale SoC’s up to billions of gates
• Working with package/substrate designers to ensure signal and power integrity