Company Overview:
InspireSemi has developed an advanced, next generation accelerated computing platform for HPC, AI, graph analytics and other compute-intensive applications. This supercomputer-cluster-on-a-chip has 1,536 high-performance 64-bit CPU cores per chip, interconnected with our low latency network fabric. InspireSemi is uniquely positioned to disrupt and democratize these markets with our next generation accelerators that deliver blistering speed, energy efficiency, versatility across a range of applications, an open developer-friendly programming model, and game-changing affordability.
The successful candidates will join our small, elite team at an early stage and generate complete IC designs from RTL/netlists and third-party IP blocks, in the latest advanced FinFet process technology nodes. Our work environment provides constant opportunity to learn new skills and grow professionally, including towards leadership positions.
We offer competitive salaries, benefits, and significant equity. We have a hybrid work environment and typically meet in our Austin offices 3-4 days per week. Exceptional fully remote candidates will also be considered.
Job Responsibilities
- Floorplanning, IO pad/bump/pin placement, and power grid insertion
- Automated standard cell placement and routing
- Integrating hierarchal block designs including third-party IP
- Power, performance, and area optimization, working closely with RTL designers
- DRC and LVS verification/debugging
- EM/IR analysis
- Timing signoff
Qualifications
- BS or higher degree in electrical or computer engineering
- 5+ years of experience in automated digital IC design from RTL to GDS
- Experience with advanced process nodes from 12nm down to 4nm and lower
- Excellent EDA tool scripting and problem-solving skills
- Fundamental understanding of electronic design principles and process design rules
Preferred Experience
- Cadence APR toolchain (Genus, Innovus, Pegasus, etc)
- Implementing high-performance CPU cores
- Designing with high-speed digital interface blocks such as PCIe, DDR and HBM
- Designing and verifying large-scale SoC’s up to billions of gates
- Working with package/substrate designers to ensure signal and power integrity