In this position, the successful candidate will be responsible for the design, development and delivery of standard cell and custom library circuits in the latest advanced FinFet process technology nodes.
- Design standard or custom digital logic and sequential cells or macros at the transistor level
- Circuit optimization for power, performance, and area optimization.
- Perform near threshold voltage circuit design.
- Simulateand analyze circuit designs using industry standard simulation tools.
- Benchmark circuit performance.
- Generate and verify library EDA models.
- Run regression and other quality checks on library deliverables.
- Interface with physical designers to facilitate cell layouts.
- Interface with design teams to support their requirements.
- 5+ years digital or analog design experience.
- Experience with Virtuoso and Hspice.
- Experience with low-voltage, low-power design.
- Understanding of cell layout or physical design.
- Experience in transistor level circuit design.
- Familiar with variation analysis.
- Experience in advanced technologies preferred.
- Familiarity with standard cell characterization and Liberty format preferred.
- Perl, TCL, Python, and/or Shell scripting skills are a plus.
Highly Preferred Qualifications
- Experience working with ADCs and DACs, and familiarity with a variety of architectures.
- Design experience with some of the following: SerDes, PLLs, bandgaps, current reference generation circuits.
Education & Experience
- BSEE / MSEE is required.
- Strong interpersonal and communication skills.
- Highly organized and detail oriented.