In this position, the successful candidate will work with circuit designers to produce layouts for analog, custom digital and mixed signal circuits in the latest advanced FinFet process technology nodes.

Job Responsibilities

  • Create layouts for digital, analog, and mixed signal circuits: standard cells, PLLs, ADC, DAC, Bandgap ref and other high-speed connectivity circuits.
  • Circuit optimization for power, performance, and area optimization.
  • Analyze floorplans and complex circuits with circuit designers.
  • Work with circuit designers to plan/schedule work and negotiate any necessary layout tradeoffs.


  • 5+ years of experience with custom analog layout design in CMOS processes, preferably with FinFET nodes.
  • Working knowledge on various analog IP blocks: Standard Cells, PLLs, ADC, DAC, Bandgap ref and other high-speed connectivity circuits.
  • Experience with advanced analog layout strategies, including matching, signal shielding, design for EM and IR.
  • Experience with top level layout concepts and strategies, including block level pin placement and top-level critical signal routing.
  • Experience with hierarchical/modular layout design.
  • Extensive knowledge and understanding of physical verification tools and flows, including LVS, DRC, ERC, Antenna checks, XOR checks, etc.
  • Good understanding of parasitic RC delay, signal integrity and EM
  • Chip planning and block implementation.
  • Ability to estimate layout schedule for a given circuit, layout planning and provide early feedback to circuit design engineers etc.

Highly Preferred Qualifications

  • Expertise on Cadence virtuoso custom/analog layout platform.
  • Layout experience with some of the following: ADC, DAC, Standard Cells, SerDes, PLLs, bandgaps, current reference generation circuits.

Education & Experience

  • BSEE / MSEE is required.

Additional Requirements

  • Strong interpersonal and communication skills.
  • Highly organized and detail oriented.
Job Category: engineering
Job Type: Full Time
Job Location: Austin

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